Reversible Logic Synthesis for NISQ-Era Quantum Computers


Fereshte MozafariPhD student, EPFL-IC-LSI

Mathias SoekenPost-doc, EPFL-IC-LSI 

Giovanni De Micheli, Professor, EPFL-IC-LSI


Quantum computing has been expanded in the last decades due to its abilities in various applications, such as integer factorization or quantum simulation. With the release of quantum computers with 50 and 72 qubits by IBM and Google, respectively, we are expecting to have quantum computers including hundreds of qubits in the future. This upcoming period is termed Noisy Intermediate Scale Quantum (NISQ) era. In the NISQ era all logical qubits are implemented by physical qubits without Quantum Error Correction (QEC). NISQ hardware is constructed of a certain coupling graph and a subset of theoretically possible quantum gates can be directly implemented on it. Therefore, NISQ hardware is not as perfect as the quantum program model. Inserting extra SWAP gates is required to implement algorithms on the NISQ hardware and satisfy coupling constraints for 2 or more qubits gates.


This PhD project aims to altering quantum program to satisfy coupling constraints of NISQ hardware. This modification is considered on synthesis or mapping levels with the purpose of reducing the total gate volume and depth of quantum circuit.

Main publications available here.