Michele De Marchi

Thesis title: Polarity Control at Runtime: from Circuit Concept to Device Fabrication

Year: 2015

Fabrication of Double Gate Silicon Nanowire FETs with run-time Polarity Control

Michele De Marchi, PhD student, EPFL-IC-LSI
Pierre-Emmanuel Gaillardon, Post-doc, EPFL-IC-LSI
Giovanni De Micheli, Professor, EPFL-IC-LSI


Present-day CMOS circuit design has witnessed an exponential increase of performance ongoing for the last fifty years. This has translated in both the transistor devices becoming smaller and more difficult to manufacture, and the circuits becoming hugely complex. At the same time, strong physical limitations to further downscaling of device dimensions is stimulating the search of alternative devices, such as nanowire or carbon based devices, which could overcome these difficulties.


In this project, we envisioned the introduction of silicon nanowire based functionality enhanced devices as a substitute of conventional MOSFET devices. Specifically, we fabricated devices which can change polarity (n or p-type) at run-time by simply changing the bias of a polarity gate structure (see figure). The devices are fabricated with a top-down approach, directly enabling large scale integration using silicon nanowires as the natural enhancement of FinFETs for best electrostatic control of the conducting channel.
At the same time, the added degree of freedom given by polarity control enables the fabrication of complex circuits using less resources than conventional CMOS, with the XOR logic gate requiring only 4 transistors and a full adder requiring only 8.

Overall, this novel device structure allows us to produce an efficient device and circuit co-optimization, where a slightly more geometrically complex device than a MOSFET is shown to be more efficient than CMOS when also the circuit architecture is taken into account.


A 3D conceptual device model: the Polarity Gate bias sets the device polarity. In green, Source and Drain pillars sustain a horizontal nanowire stack which forms the channel.

SEM micrograph of the fabricated devices. The color highlighting corresponds to the conceptual model.

The measured Id-Vcg device characteristic for different Vpg biases. The devices can work as either n or p-type, with high symmetry and steep subthreshold slopes.

Measured 2-transistor circuit implementing a XOR logic function. This characteristic cannot be obtained with conventional MOSFETs, and is enabled by the polarity control degree of freedom.



  • Demonstrate the advantage of this transistor in terms of fabrication simplicity and potential for future circuit applications.
  • Fabricate small logic circuits to confirm the validity of the approach.


Selected publications:

M. De Marchi, D. Sacchetto, S. Frache, J. Zhang and P.-E. J. M. Gaillardon et al. Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs. International Electron Devices Meeting (IEDM), San Francisco, California, USA, 2012.

M. De Marchi, H. Ben Jamaa and G. De MicheliRegular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications. IEEE/ACM International Symposium on Nanoscale Architectures (Nanoarch’10), Anaheim, California, USA, 2010.