Reliability evaluation of the emerging technologies
Hassan Ghasemzadeh, PhD Student, EPFL-IC-LSI
Pierre-Emmanuel Gaillardon, Post-doc, EPFL-IC-LSI
With the current trend of dimension shrinkage in conventional CMOS technology, the modeling and simulation of the feature devices and circuits must consider reliability. Accurate and low-cost simulation of the process variations and possible defects is very critical especially for emerging technologies.
In the lack of mature compact models for emerging devices, TCAD provides the opportunity of low cost process variation simulations. With aggressive moving toward deep nano-scale, the execution time of the common variation analysis technique such as Monte Carlo exponentially grows according to the number of device parameters. Therefore, parameter reduction techniques become very important for fast simulation. Moreover, enhancing the time complexity of computations in 3-D TCAD is necessary. Currently, trade-off between time complexity and accuracy is the greatest challenge of reliability and variability models.
From the test perspective, it is also not obvious that the common fault models such as stuck-at-0 and stuck-at-1, which are extensively used for bulk CMOS technology, are able to reveal the fabrication defects for emerging nano-devices. Therefore, a practical method is necessary to extract an appropriate fault model for the target technology which considers device fabrication process.
To achieve these goals, this project is focusing on developing a novel methodology for reliability analysis of the future integrated circuits. This methodology consists of two parts: first, finding the main sources of variations for a new technology and time complexity reduction of process variation analysis using this information. Second, developing fault models based on the fabrication process of the target device which can be used for test purpose.