Novel Logic Synthesis


Pierre-Emmanuel Gaillardon
Post-doctoral Researcher

Emerging device technologies

Luca Amaru
PhD Student

EDA tools

PhD project page:

Electronic Design Automation for Emerging Technologies and Applications

Hassan Ghasemzadeh
PhD Student


PhD project page:

Reliability evaluation of the emerging technologies

Novel Logic Synthesis

Nowadays, EDA tools face challenges tougher than ever. On the one hand, design goals in modern CMOS technology approach the frontier of what is physically achievable. On the other hand, post-CMOS technologies bring new computational paradigms and logic devices for which standard EDA tools are not suitable.

At the LSI laboratory, we believe that new research in logic synthesis is key to handle this situation. In particular, innovative logic data structures and optimization techniques will be decisive. By using expressive Boolean primitives, the efficacy of logic optimization within a standard synthesis flow can be sensibly improved. This enables smaller, faster and cheaper CMOS circuits. Considering post-CMOS technologies, novel logic abstractions and synthesis techniques capable to fully exploit a device expressive power are the technology enablers. This is because they allow designers to validate a post-CMOS technology on large-scale benchmarks.

To answer this challenge, we develop new data structures and optimization methods based on majority and biconditional logic connectives. We have demonstrated tremendous improvements in contemporary CMOS design, especially for arithmetic circuits. Indeed, majority and biconditional are the basis for arithmetic. Moreover, we have shown that our majority and biconditional data structures are natural and native design abstraction for a promising class of post-CMOS technologies. Specific examples include, but are not limited to, silicon nanowires, carbon nanotubes, graphene, nanorelays, resistive random-access memory, spin-wave devices, organic FETs, quantum-dot cellular automata, nanomagnets, reversible logic, and many others.


Static Random Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) are more flexible than Application-Specific Integrated Circuits (ASICs) at the cost of 20× bigger area, 4× longer delay, and 12× higher power consumption approximately. The drawbacks of FPGAs lie in the expensive routing architecture, which accounts for about 70% of the area, 80% of the delay and 60% of the power of the entire chip. Power consumption is a serious barrier for the distribution of FPGAs in a large set of consumer applications, i.e., Ultra-Low Power (ULP) System-on-Chip (SoCs). Previous works demonstrate low-power SRAM-based FPGA designs where a low supply voltage is employed to save up to 50% of the power consumption. However, low-power SRAM- based FPGAs generally suffer from large delay degradation (up to 2×).

Comparisons between a standard SRAM-based FPGA and the considered RRAM-based FPGA


EDA for Nano

The recent development of Resistive Random Access Memories (RRAMs) opens opportunities in advancing the FPGA technology with high density, performance and excellent energy efficiency. Typically, around 40% of the transistor area in SRAM-based FPGAs is occupied by configuration memories.    However,    RRAMs    can    be monolithically fabricated within the Back-End-of-Line (BEoL) metal lines. This allows us to move the configuration memories onto the top of the transistors, thereby increasing the integration density, and to shorten the metal interconnections. Furthermore, SRAM-based FPGAs have to be configured every time the system is powered on due to the volatility of SRAMs. Overwhelming Static Random Access Memories (SRAMs) intrinsically, RRAMs hold storage when powered down and consume zero leakage power in sleep mode. Using RRAMs as standalone memories, FPGAs can benefit a ~50% power reduction from instant power-on and normal power-off, compared to SRAM-based counterparts. Furthermore, RRAMs motivate the exploration of novel FPGA architectures whose routing structures are directly employing RRAMs in the data path. In the novel architectures, RRAMs play the role of both configurable memories and programmable switches. The Low-Resistance State (LRS) of RRAMs provides down to 75% lower on-resistance than pass transistors, and thus reduces the delay of critical path. Finally, the novel routing elements demonstrate very good properties under reduced power supply conditions. Indeed, RRAM-based multiplexers can operate at near-Vt with significant power reduction for almost no performance compromise. Such blocks can be exploited advantageously to design ultra-low-power FPGAs.

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

The continued feature-size scaling trend for extending Moore’s law has faced significant challenges from short-channel effect and leakage power phenomena. To discover possibilities for further performance and functionality, a huge research effort has been devoted on innovative device structures. FinFET transistors, as an example of multigate devices, are successfully replacing bulk CMOS transistors beyond the 22nm technology node. Following the trend toward one-dimensional structures, Silicon NanoWires (SiNWs) with Gate-All-Around (GAA) structures provide an even better electrostatic control over the channel and reduce leakage current.

Beyond 45 nm, many devices exhibit Schottky characteristics at source and drain contacts such as Silicon Nanowires (SiNW)s, carbon nanotubes, and graphene transistors. These junctions demonstrate ambipolar behavior, i.e., they support the flow of both n and p type carriers. While ambipolarity is usually suppressed in the fabrication process to provide unipolar devices, it can be used to enhance logic functionality. Double-Gate (DG) and Three-Independent-Gate (TIG) devices based on SiNWs are examples of devices with enhanced functionality

To reveal fabrication defects and circuits malfunctioning, a number of structural fault models for planar single-gate CMOS and FinFET technologies have been proposed and proved to be efficient. For instance, stuck-at, delay, stuck-open, and bridging faults are among the most commonly-used models for CMOS technology. For FinFETs, a few number of studies have been conducted in modeling defects such as floating gates and shorts, stuck-open/stuck-on, and Gate Oxide Short (GOS). These studies revealed the deficiency of current CMOS fault models for detecting defects in FinFET circuits, and necessitated a new fault model for test generation purposes.

We have investigated the specific faults of Controllable Polarity Silicon NanoWire FETs (CP-SiNWFETs) by inductive fault analysis methods.  The possible defects that can occur during CPSiNWFETs fabrication process have been modeled. Using the obtained defect model, we have investigated the functionality and the performance of various CP logic gates in the presence of defects. The results confirmed the inefficiency of the traditional fault models for covering the defects in CP-SiNWFET technology. A hybrid fault model that contains stuck@ p type and n type, has been introduced for CP-SiNWFETs and its efficiency is verified for specific faults that occur in devices fabricated under this technology.