High-expressive-power logic architecture
It has been shown that independent double gate ambipolar FET geometries, using CNTs or SiNWs, can be exploited to create electrostatically polarizable (n or p-type) transistors. We take advantage of the unique feature of these devices to explore a novel logic architecture in which binate functions (e.g. XOR) can be implemented with lower resources than in standard CMOS. Our logic architecture is static and complementary, thus combining the advantages of conventional CMOS, such as robustness to noise, low power consumption and design simplicity to the peculiar high expressive power given by runtime polarizable FETs.
Polarizable FET regular fabric design
Device and logic cell level regularity is a highly regarded feature in circuit design at the nanoscale, contrasting physical and performance variability and reducing device failure rate. We extend the analysis of the static logic concept based on ambipolar FETs by evaluating its performance in regular fabric circuit design. We construct complex logic gates, each of which can be implemented in a regular fabric, like a gate array or an FPGA. Since our gates can implement complex functions with low resources compared to classic logic gates such as the Actel ACT1 or n-input LUTs, we can obtain more compact and expressive regular circuits.
Polarizable FET physical design
In order to fully exploit the properties of independent double gate ambipolar FETs, advanced architectures such as gate all around, stacked SiNWs can provide optimal electrostatics and polarity control properties. We explore these architectures, evaluating their physical properties and device performance. Large-scale regularity is especially exploited to reduce device variability and simplify circuit design.