Logic Synthesis and Digital Design

People

Giovanni De Micheli
LSI Director and Professor

 

 
Mathias Soeken
Postdoctoral Researcher

Logic Synthesis

 

 

Heinz Riener
Postdoctoral Researcher

Logic Synthesis

 

 

Cunxi Yu
Postdoctoral Researcher

Logic Synthesis

 

 

Winston Jason Haaswijk
PhD Student

Logic Synthesis

PhD project page:

Applications of Biconditional and Majority Logic

Xifan Tang
PhD Student

FPGA Architectures

PhD project page:

Architecture Exploration and CAD for RRAM-based FPGA

Eleonora Testa
PhD Student

Logic Synthesis

 

Giulia Meuli
PhD Student

Logic Synthesis

 

Bruno Schmitt
PhD Student

Logic Synthesis

 

Logic Synthesis

Nowadays, EDA tools face challenges tougher than ever. On the one hand, design goals in modern CMOS technology approach the frontier of what is physically achievable. On the other hand, post-CMOS technologies bring new computational paradigms and logic devices for which standard EDA tools are not suitable. Logic synthesis is directly located at the intersection of application and technology. Its task is to transform a functional and technology-independent description of an application (e.g., a microprocessor) into a low-level description that takes technology and architecture constraints into account (e.g., gate libraries and architectures). Typical considered optimization criteria are physical area, delay, and fabrication costs. At LSI, our research objective is to enable ideal tradeoffs at this interface between technology and application. Our findings allow designers to build better hardware with lower costs.

At LSI, we believe that research in logic synthesis is key to address this challenge. In particular, innovative logic data structures and optimization techniques will be decisive. By using expressive Boolean primitives, the efficacy of logic optimization within a standard synthesis flow can be significantly improved. This enables smaller and faster CMOS circuits at lower costs. Considering post-CMOS technologies, novel logic abstractions and synthesis techniques capable to fully exploit a device expressive power are the technology enablers. This is because they allow designers to validate a post-CMOS technology on large-scale benchmarks.

We develop new data structures and optimization methods mainly based on majority and comparator logic connectives. We have demonstrated tremendous improvements in contemporary CMOS design, especially for arithmetic circuits. Indeed, majority and comparators are the basis for arithmetic. Moreover, we have shown that majority data structures are natural and native design abstraction for a promising class of post-CMOS technologies. We develop new optimization algorithms based on modern algorithms. As one example, we use SAT solvers at the core of our logic synthesis algorithms.

At LSI, we are maintaining the open source toolkit CirKit . CirKit contains implementations of many logic synthesis algorithms. It is used to share algorithms and experimental results with other researchers and as a collaboration tool for research.

EDA for FPGAs
Static Random Access Memory (SRAM)-based Field Programmable Gate Arrays (FPGAs) are more flexible than Application-Specific Integrated Circuits (ASICs) at the cost of 20× larger area, 4× longer delay, and 12× higher power consumption approximately. The drawbacks of FPGAs lie in the expensive routing architecture, which accounts for about 70% of the area, 80% of the delay and 60% of the power of the entire chip. Power consumption is a serious barrier for the distribution of FPGAs in a large set of consumer applications, i.e., Ultra-Low Power (ULP) System-on-Chip (SoCs). Previous works demonstrate low-power SRAM-based FPGA designs where a low supply voltage is employed to save up to 50% of the power consumption. However, low-power SRAM- based FPGAs generally suffer from large delay degradation (up to 2×).

EDA for Quantum Computing
We develop elaborated tool flows that enable to design quantum computers as efficient and convenient as we design classical computers today. Designers and application engineers should be able to work in a technology-independent manner, and designs should be sustainable and be reused over a longer time, even when architecture profiles are changing (which is frequently the case in quantum computing today). For this purpose, logic synthesis tools and algorithms are developed that map to efficient technology-dependent designs while considering cost tradeoffs. We have developed several such design flows. Programs written in standard hardware-description languages (VHDL and Verilog) are input to the design flows that will map them to quantum circuits based on different cost criteria. Key data structure in these design flows are reversible circuits, which are circuits that only allow reversible computation.

Our open source toolkit RevKit  contains implementations of reversible synthesis algorithms and design flows both developed at the laboratory as well as many other state-of-the-art algorithms that were proposed in the recent years.