**** Semester Project ****
Contact: Dr. Federico Angiolini, Senior Scientist, EPFL-IC-ISIM-LSI
Project description:
Ultrasound imaging is widespread in diagnostics in all medical fields. Although the basic technology has been available for a long time, recent developments go in the direction of (i) 3D imaging (a 3D volume is acquired at every frame, instead of a customary 2D section), (ii) portable imagers. The first development enables the reconstruction of stunning images, which is specially useful in the context of obstetrics, where the fetus can be shown with clarity, and in cardiology, where valve operation and chamber volumes can be studied with much greater ease and precision. Unfortunately, 3D imaging requires massive computing resources, and today’s 3D machines, which are generally only available in hospitals, are expensive, bulky, and power-hungry, requiring several hundreds of watts. This conflicts with the second trend, which aims at small, portable, battery-operated imagers. These are conceived for widespread use both in medical cabinets and on-the-field (e.g. emergency rescue operations), where compactness, ease of use, and cordless operation are welcome improvements. Portable ultrasound imagers are on sale today, but they have limited image quality, and only 2D capabilities.
In this project, we try to improve the state of the art by designing an imager architecture that, while capable of tackling 3D imaging, can be fitted into one or few FPGAs. The overall goal is to demonstrate that a 3D imager can be made to work on a power budget compatible with battery operation.
Project tasks:
- Getting familiar with the basic principles of ultrasound imaging.
- Expanding a pre-existing FPGA architecture, that encompasses the kernel of the ultrasound imaging algorithm, to add more capabilities. This includes a) Verilog design, b) cycle accurate simulation of the design, c) mapping onto an FPGA board.
- Exploring the scaling opportunities to fit the design, of course with varying capabilities, onto FPGAs of varying size.
Eligibility requirements:
The eligibility requirements for this project are:
- VLSI design background
- Familiarity with HDL languages (VHDL or Verilog)
- Basic knowledge of FPGA architectures and flows