Power Models and Related CAD Tool for DRAM Memory

***Archived: This is a past project,  it is not on offer at the moment!***


Project Description:
Memory constitutes a basic component of any non-trivial modern computing system. Several types of volatile, such as DRAM, SRAM and non-volatile memory, such as ROM and FLASH exist. Dynamic memory (DRAM) is preferred over other types of memory (e.g., static RAM (SRAM)), since this type of memory supports particularly high densities; a fundamental prerequisite for high-performance computing systems. This situation is due to the simple structure of the elemental memory cell consisting of a transistor and a capacitor. The charge stored in this capacitor corresponds to a logic value of ‘0’ or ‘1’ for a binary digit (bit).

Although the integration of DRAM memory cells can be extremely dense, charge leaking mechanisms complicate the design and correct operation of DRAM memory. In addition, the increasing size of the memory modules further hinders the ability to sense large capacitive lines and accurately render the bit information. Consequently, to guarantee the correct operation of the DRAM, the stored information is periodically refreshed. The frequency of the “refresh” operation depends both on the design and manufacturing technology of the memory. Due to these issues, a variety of DRAM circuit designs exists related to the memory architecture, the sensing circuitry, and the addressing scheme as well as the DRAM fabrication process. Furthermore, several design and technology parameters determine the performance and, specifically, the power dissipated by a DRAM module.

The development of appropriate power consumption models is of primary importance as these models can be used to determine the required refresh rates. Inaccurate prediction of the refresh cycles can decrease the speed of the memory and increase the power consumption and the bit error rates. Thus, the objective of this master thesis project is to develop power models that combine an as broad (and disparate) as possible set of those parameters that primarily determine the energy dissipated by a DRAM memory. These parameters can include, for example, the organization of the memory blocks (which determines the capacitance that is charged/discharged at each write/read operation), technological parameters as provided by different memory vendors etc. The power models can be either analytic or to combine analytic expressions and simulations. Valuable information can also be obtained on-line by the memory vendor websites. The developed power consumption models will be integrated to a CAD tool to support the exploration of diverse tradeoffs that affect the total power consumed by a DRAM memory module.


  • Exhaustive study of existing literature on modeling the power consumption of a DRAM memory. Further information may be obtained from the websites of memory vendors
  • Development of power models for DRAM memories that include primary physical and design parameters
  • Verification of the models through existing “hard” DRAM macros provided by different design kits
  • Integration of the models within a computer aided design tool


  • Basic knowledge of memory circuit design and the related charge leakage mechanisms
  • Basic knowledge of Cadence and/or SPICE design tools
  • Some knowledge on low power techniques and methods in integrated systems
  • Sufficient programming skills in C, SystemC, and/or HDL languages (Verilog, VHDL)

This project was supervised by Vasilis Pavlidis.

***Archived: This is a past project,  it is not on offer at the moment!***