Design Methodologies and Algorithms for Repeater Insertion in 3-D Integrated Systems

***Archived: This is a past project,  it is not on offer at the moment!***


Project Description:
The miniaturization of electronic systems has enabled a steady increase in the performance of these systems. This increase has predominantly been achieved by shrinking the physical dimensions of the transistors. The simultaneous scaling of the interconnects, however, can degrade these advantages due to the increasing resistance of the on-chip wires. To mitigate this issue, several techniques to improve the interconnect performance. An efficient and, perhaps the most common of these techniques is repeater insertion. The fundamental concept of this technique originates from the telephone systems, where repeaters are interspersed along the telephone lines. Similarly, on-chip repeaters are inserted along long wires to amplify and recover the propagated signal. A plethora of repeater insertion tech-niques and algorithms have been developed within the realm of two-dimensional (2-D) integrated circuits. No methods whatsoever for inserting repeaters in 3-D integrated systems have been developed. An example of a four plane 3-D IC is shown below.


Schematic of a 3D IC consisting of four physical planes

This observation constitutes the goal of this project. The repeater insertion problem for 3-D ICs has several constituents, which significantly differentiate it from the 2-D case. For instance, each plane can be manufactured with a different fabrication process resulting in disparate interconnect impedance characteristics within each plane. In addition, the interplane nets include the vertical interconnects, which are substantially different from the horizontal interconnects within each plane.
New methods and techniques will be developed as part of this project to insert repeaters and efficiently improve the performance of 3-D ICs, while satisfying various constraints, such as bandwidth and power constraints. Particular emphasis will be placed on the inherent diversity of 3-D integration. To demonstrate the efficiency of the proposed methods and algorithms, the developed methodologies will be applied to different interconnect networks through SPICE or Cadence.

Project tasks

  • Literature search related to repeater insertion techniques for 2-D ICs
  • Analysis of the requirements and the specific electrical characteristics of the interconnects in 3-D ICs
  • Development of repeater insertion techniques and algorithms for interplane nets in 3-D ICs
  • Analytic validation of the efficiency of the techniques and low complexity of the algorithms with Matlab and/or C
  • Application of the developed methodologies to several interconnect networks with the Cadence or SPICE design tools


Eligibility requirements

  • Basic knowledge of circuit analysis and algorithms
  • Good knowledge of Cadence and/or SPICE design tools and Matlab or C/C++ programming language
  • Some knowledge on interconnect modeling is a plus


This project was supervised by Dr. Vasilis Pavlidis.


***Archived: This is a past project,  it is not on offer at the moment!***