Modeling and Design of Clock Skew Insensitive Clock Distribution Networks for 3-D ICs

***Archived: This is a past project,  it is not on offer at the moment!***


Project Description:
The driving force of semiconductor industry for the several past decades, namely transistor scaling, faces nowadays multiple challenges. These difficulties have triggered a quest, both within academia and industry, for innovative design paradigms that support the development of future integrated systems with enhanced performance characteristics and functionality. Three-dimensional (3-D) integration emerges as a potent technology, which embodies these requirements. A 3-D circuit typically consists of several physical planes, where each physical plane includes a transistor layer and multiple metal layers for interconnects. An example of a 3-D circuit is illustrated below:

Schematic of a 3D IC consisting of four physical planes

Although simple prototypes of 3-D circuits have been demonstrated with encouraging results, several challenges need to be overcome to promote 3-D integration to a mainstream technology. One global challenge related to synchronous digital 3-D circuits is to distribute the clock signal within a multiplane integrated system, while satisfying specific clock skew constraints (Clock skew is, in general, defined as the difference in the arrival time of the clock signal between two sequential elements (e.g., flip-flops)).

The primary objective of this project is to determine the clock skew produced within and among the physical planes of a 3-D circuit. To fulfill this task the within die (intradie) and die-to-die (interdie) process variations will be considered. Performance variability within a circuit is, for example, due to the transistor voltage threshold, the transistor channel length, and the interconnect and dielectric thickness variations. Both deterministic and probabilistic models for 3-D circuits will be developed (or adapted) to describe these variations. The developed models will be applied to different clock distribution topologies to determine the produced clock skew within each topology. Based on these results, new clock distribution topologies for 3-D ICs will be proposed. These topologies will be compared in terms of clock skew and power consumption through Cadence or SPICE.

Project tasks
•    Exhaustive study of existing modeling approaches for interdie and intradie process variations
•    Development of process variation models for 3-D circuits
•    Design and comparison of clock skew insensitive clock distribution networks for 3-D ICs

•    Sufficient knowledge of random processes and probabilities
•    Basic knowledge of synchronization issues in digital circuits
•    Basic knowledge of Cadence and/or SPICE design tools

This project was supervised by Vasilis Pavlidis.


***Archived: This is a past project,  it is not on offer at the moment!***