Cross-Talk in Fully-Depleted Silicon Nanowire Arrays

***Archived: This is a past project,  it is not on offer at the moment!***

Project Description:

The crossbar architecture is a simple and useful arrangement of parallel wires in two arrays which are laid perpendicularly to each other. At the cross-areas of these two arrays storage devices can be placed and programmed in order to allow or stop conduction through the crossing wires (Fig. 1). This architecture can implement logic functions, memory and interconnections. In addition to its advantages in terms of function and area, the crossbar circuits can be realized in all known technologies and particularly in the emerging bottom-up technological approaches involving molecular storage devices and sub-lithographic wires.

In our technological approach, we consider the nanowires fabricated as polycrystalline silicon (poly-Si) spacers separated by silicon dioxide (SiO2) spacers. The multispacer formed by successive poly-Si and SiO2 spacers represents a layer of parallel poly-Si and SiO2 nanowires. The conduction through the poly-Si nanowires is controlled by a unique gate electrode patterned on the nanowire array (fig. 2). In order to control the nanowires separately, they need to be differentiated. Several ways of differentiation are allowed within this technology, including nanowire height, doping level and gate oxide thickness.

The final result of any way of differentiation cited above is a modulation of the threshold voltage (VT) of the transistors formed by the gate electrode and the Si nanowires, called Silicon Nanowire Field Effect Transistor (SiNW FET). Since the separation between two successive SiNW FETs is a thin SiO2 nanowire of a few tens of nanometer of width, two adjacent nanowires can influence the conduction through the central nanowire. Finally, any SiNW FET can be controlled not only by its gate electrode but also by the bodies of the adjacent SiNW FETs; which is called cross-talk.

The purpose of this project is to study the field-effect device formed by a Si nanowire channel, a top gate electrode and two lateral electrodes. A device simulator will be used in order to investigate the following effects:

  • Dependency of VT on the differentiation parameter (nanowire height, doping level or gate oxide thickness).
  • Dependency of VT on the adjacent devices (cross-talk between SiNW FETs).
  • Device operation in full-depletion mode: Conditions for fully-depleted devices (size, doping level) and the controllability by a second back-gate will be investigated. 


Project Organization:

  • Literature research on suitable model for considered device (current conduction, VT expression…)
  • Implementation of the chosen model with a device simulator
  • Investigation of the impact of the differentiation parameters on VT
  • Investigation of the cross-talk between adjacent SiNW FETs
  • Study of selective conduction through nanowires (vs. differentiation parameters, cross-talk and back-gate)



  • Knowledge about device physics
  • Basic knowledge of device simulator (DEVISE of Synopsis or similar tools)

This project was supervised by Haykel Ben Jamaa.


***Archived: This is a past project,  it is not on offer at the moment!***