Network-on-Chip (NoC) Interconnection Monitoring in a Multi-Processor System-on-Chip (MPSoC) FPGA-Based Emulation Platform

***Archived: This is a past project,  it is not on offer at the moment!***

Project Description:

With the growing complexity in consumer embedded products, a new-born generation of System-On-Chip (SoC) architectures consisting of complex integrated components communicating with each other at very high-speed rates is being envisioned. One of their main design challenges will be the prototyping of SoCs consisting of hundreds of processing cores (Multi-ProcessingSoC or MPSoC). Within this context, it is perfectly plausible to believe that the use of cycle-accurate simulations for studying efficient intercommunication mechanisms of a heterogeneous SoC design made of dozens of IP-cores will not be feasible due to the additional overhead for handling all the concurrent signals. Moreover, traditional designs using a single shared bus or not even a hierarchy of buses will become unaffordable due to their poor scalability with system size and their shared bandwidth between all the cores attached to them.

To overcome these problems of efficient modeling of MPSoC systems we propose the use of FPGA emulation, which attains significant speedups compared to cycle accurate MPSoC simulators. Additionally, to help to solve the problems of scalability and complexity of interconnection design, we include the use of Network-On-Chip (NoC) interconnection paradigm. This technology extrapolates some concepts from computer networks to on-chip interconnection of IP-cores and has created a new complete set of design issues to consider. Among the most important ones we can mention the choice of packet sizes and the internal architecture of on-chip routers or switches. In all these cases, important questions come up regarding the scalability of the solutions and the waste of intercommunication channels, which are still to be answered. Also, the range of NoC interconnection topologies is very broad (e.g. meshes, torus, bi-directional rings, fat-tree or application-specific topologies). However, presently no complete framework exists to evaluate in detail the features of the previous topology and characteristics in a reasonable amount of time.
The purpose of this project is to extend the current MPSoC FPGA-based emulation platform available at LSI/EPFL with a consistent mapping flow from existing NoC tools in such a way that a complete set of statistics can be extracted for real-life applications. To this end, the student needs to study how to efficiently map the existing VHDL/Verilog code from NoC solutions onto a Xilinx Virtex-II Pro FPGA. Then, a complete set of statistics that monitor the internal state of the NoC needs to be extracted and sent using the available Ethernet connection on the FPGA to an external host PC. Using this information, several run-time tuning policies for congestion-aware routing algorithms or error prevention schemes can be considered and implemented. The proposed project implies the use of latest Xilinx hw/sw co-design tools for FPGAs (e.g. Xilinx Embedded Development Kit) and software debugging tools (Xilinx Chipscope), as well as additional hardware simulation tools (Mentor Graphics Modelsim) and software toolflows for current embedded processors (e.g. GCC crosscompiler for PowerPC).

Tasks :

The tasks expected by the student developing this project are very briefly described in the following:

  • Study of the Xilinx Virtex-II Pro HW/SW toolflow.
  • Study of existing NoC compiler Xpipes from Stanford University, USA and Bologna University, Italy.
  • Modification toolflow of Xpipes compiler to generate correct Verilog/VHDL code for the Virtex-II Pro FPGA.
  • Inclusion of additional HW modules to extract the statistics in the original NoC design.
  • Bidirectional communication of statistics via an Ethernet link to a host PC.
  • Extension of current software in the MPSoC emulation platform to extract the new statistics
  • Implementation and exploration of several NoC-based solutions to verify the correct behaviour of the system.


This project involves knowledge of various aspects of digital system designs. Its requirements are enumerated below:

  • Advanced programming knowledge of the Hardware Design Languages, such as, VHDL or Verilog.
  • Basic knowledge about computer architecture and elementary components (e.g. processors, buses, etc.)
  • Basic knowledge is advisable about software development in C and hardware description in SystemC.


This project was supervised by David Atienza.


***Archived: This is a past project,  it is not on offer at the moment!***