***Archived: This is a past project, it is not on offer at the moment!***
Project Description:
Rapid advances in semiconductor manufacturing technologies have resulted in an ever increasing number of components to be implemented on a single chip. Such System-on-a-Chip (SoC) designs have very demanding communication requirements between individual components. Traditional bus-based communications systems that connect multiple blocks and span a large portion of the chip have become a performance bottleneck. One solution to these problems is to use an on-chip interconnection network, commonly known as Network on Chip (NoC).
There are different approaches to designing NoCs. Over the years members of the Integrated Systems Laboratory (LSI) have been instrumental in developing successful NoC system. The core of the system is based on a library of highly parametrizable network components called Xpipes. A design flow, called Sunfloor, is able to map a given application using components from the Xpipes library. This design flow includes the Xpipescompiler which will perform instantiations of the Xpipes components
In this project, a complete NoC system developed with the Sunfloor methodology will be implemented on an ASIC. The ASIC will then be sent to manufacturing. The performance figures of the final design will be used to valuate the validity of the NoC approach.
Furthermore, it will be possible to optimize and refine the design flow for real-woprld applications.
The ASIC development will be made in partnership with the Integarted Systems Laboratory (IIS) of the ETH Zurich, which has vast experience in digital IC design.
Tasks:
- Develop a NoC system using the Sunfloor design flow.
- Map the resulting system on an ASIC (0.18 or 0.13um CMOS).
- Perform the back-end design flow and send the design to fabrication.
- Provide real-world performance numbers for the design flow.
- Verify the validity of the NoC approach.
Requirements:
- Experience with Hardware Design Languages (VHDL)
- Knowledge on VLSI architectures and design
- Willing to work in Zurich at the Integrated Systems Laboratory.
This project was supervised by Frank K. Gürkaynak.
***Archived: This is a past project, it is not on offer at the moment!***