***Archived: This is a past project, it is not on offer at the moment!***
Project Description:
In the semiconductor industry, the transistors size is scaling down following Moore’s law. This enables the integration of more and more devices on a single chip. In particular, it has been observed that in forthcoming SoCs many types and a large amount of memories will take a very significant part of the die to minimize off-chip communication.
Power breakdown for deep-submicron technology (e.g. 65nm) shows that leakage is becoming a major contributor of the total consumption in SoCs. As memories already occupy most area on chip, leakage of memories is becoming a major contributor of the overall leakage consumption in SoCs. As a consequence, the design of power manageable memories with leakage reduction support is in great need.
Several researchers recently proposed memory designs supporting a leakage-free (also called sleep) state. However, two main issues must be taken into account. First, in this state memories are not accessible as in the normal or idle state. As a consequence, the sleep state cannot be used during normal operations. Second, it takes a non-negligible amount of time to wake-up from sleep to idle state. As a consequence, an additional latency for each memory transaction must be considered if the memory is sleeping when a request arrives.
To exploit the benefits of leakage-free state without impacting transaction latency, a suitable memory state management policy should be designed. This is more and more critical in multiprocessor systems that integrate an always increasing number of processing cores. In fact, the presence of multiple cores with several private and shared memories raises the contribution of leakage power to a high percentage of the overall power breakdown.
In this project we propose to implement a power management architecture which enables leakage management of memories without performance degradation. This power management system uses an independent inter-communication layer. In this work, we assume the data interconnection network to be a regular Network-on-Chip (NoC). The power management interconnect comes as an additional fast communication link that carries power management signals between each couple of initiators and targets (memories). It is characterized by a negligible latency (1 to 4 ns, depending on the implementation) compared to the latency of the NoC (typically more than 10 ns). Hence, notification about the request generated by the initiator can be issued before the request arrives to the target. By applying this concept to leakage power management of memories, proactive wake-up signals can be issued from the initiator to the memory to bring the memory out of sleep state just in time to be ready (in idle state) to handle the arriving request without additional latency.
Tasks:
- Study of the X-pipes NoC architecture and tool flow.
- Implementation of a synthesizable non-blocking NoC architecture dedicated to power management.
- Addition of the generation of the power management network in the X-pipes tool flow.
Requirements:
- For the RTL simulations, knowledge of SystemC (or Verilog/VHDL).
- Basic knowledge of C and C++ programming languages.
- Basic knowledge of Systems-on-Chip (SoCs) architectures.
***Archived: This is a past project, it is not on offer at the moment!***