***Archived: This is a past project, it is not on offer at the moment!***
Project Description
Three-dimensional integration is a novel design paradigm with great potential to fundamentally advance the computational functionality of modern integrated systems. Reliable communication is an important requirement for 3-D circuits. In synchronous systems, this requirement is satisfied by the design of a robust synchronization mechanism. In deep-submicrometer technologies (DSM), efficient synchronization becomes an increasingly difficult task due to the increasing process, voltage, and temperature variations (also referred as PVT variations). To manage this complexity multiple clock domains can exist within an integrated system. The demand for multiple clock domains may be more pronounced in 3-D circuits due to forecast heterogeneity and complexity of these circuits.
The objective of this semester project will, consequently, be to explore the effect of the process variations in various topologies of 3-D clock distribution networks. An existing process variation model (developed within our group) should be extended to describe process variations multi-clock domains. This model should be verified against different 3-D clock distribution networks through Cadence and/or SPICE. The outcome of this project is expected to be submitted for publication to a technical conference.
Project tasks
The tasks that this project involves are:
- Understanding of our process variation
- Modify this model to describe the behavior of multi-clock domains under process variations
- Check the model for specific and known 3-D clock distribution topologies
- Write a report (extended to a paper) describing the outcome of the project
Eligibility Requirements
The eligibility requirements for this project are:
- Random variables and processes
- Cadence and/or SPICE
This project was supervised by Vasilis Pavlidis.
***Archived: This is a past project, it is not on offer at the moment!***