***Archived: This is a past project, it is not on offer at the moment!***
Project Description:
An important issue in the design of integrated systems is the delivery of sufficient current to every device (i.e., transistors) within the system. This task is of greater importance in the case of the emerging 3-D systems that can combine vastly different circuits with disparate current and voltage requirements. To address this issue, efficient design of a power distribution system is required. A metric to quantify the robustness of these systems is the resulting power supply noise (i.e., deviation of the power supply, Vdd from the nominal levels). The deleterious effects of power supply noise include, for example, increase in the circuit delay, increase in the jitter of the clock signal, and, in extreme cases, incorrect evaluation of logic operations. Preventing these situations requires the careful analysis and understanding of the behavior of the power supply noise in multi-plane circuits.
Consequently, 3-D power distribution networks will be analyzed through Cadence and/or SPICE. The goal of the analysis is to ascertain which components of the power supply noise affect data computation or the clock distribution network. During this projects several power distribution networks will be considered, which can correspond to developmental 3-D systems.
Project tasks:
The tasks that this project involves are:
- Analysis through time and frequency domain simulations of diverse power distribution networks interconnected in a 3-D manner
- Understanding of the behavior of the power supply noise in these systems
- Suggesting ways (through some case studies) to decrease the power supply noise levers in 3-D systems
Eligibility Requirements:
The eligibility requirements for this project are:
- Basic understanding of electrical circuits and circuit analysis
- Cadence and/or SPICE simulations and scripts
This project was supervised by Dr. Vasileios Pavlidis.
***Archived: This is a past project, it is not on offer at the moment!***