***Archived: This is a past project, it is not on offer at the moment!***
Project Description:
The versatility of FPGAs has made this type of integrated circuits, increasingly popular in many applications. FPGAs are characterized by a highly regular structure where pieces of logic (also known as logic blocks, or slices) ordered in an array can be interconnected in several ways through a small group of switches (i.e., switch boxes). Since the switch boxes can be programmed to connect different logic blocks and the logic blocks can implement several logic functions, a multitude of applications can be implemented within an FGPA. This flexibility is further enhanced by the reconfigurability supported by these devices.
The goal of this semester project would be to analyze through simulations of schematics (and possibly layouts) the power components of a large set of functions implemented within the logic blocks of different FPGA devices. Logic block within FPGAs of companies and Xilinx and Altera will be considered. The involved student will delve into the subtleties of these circuits and increase his understanding on FPGAs, a useful skill for designing circuits with FPGAs.
Project tasks:
The tasks that this project involves are:
- Schematic and/or layout design of logic blocks and switch boxes with Cadence of different FPGAs
- Through evaluation of power consumed by these circuits
Eligibility Requirements:
The eligibility requirements for this project are:
- VLSI design background
- Basic knowledge of Cadence
This project was supervised by Dr. Vasileios Pavlidis.
***Archived: This is a past project, it is not on offer at the moment!***