Physical Synthesis of Benchmark Circuits through Commercial CAD Tools

***Archived: This is a past project,  it is not on offer at the moment!***



Project Description:
Knowledge of commercial electronic design automation tools is very often a prerequisite for the designer of digital circuits. These design tools are utilized at every stage of modern circuit design flows; for example during logic synthesis, technology mapping, and the place and route phase. The designer typically guides each of these steps through the various options provided by the tools or by generating scripts that more accurately instruct the different tools.

Based on the prior knowledge of these tools offered in the “VLSI II” course, the goal of this project is to allow a student to greatly expand his knowledge related to these tools and deeply comprehend the design flow of contemporary digital integrated circuits. To this end, a variety of benchmark circuits from literature (starting from the RTL description or from a circuit netlist), the involved student should implement all the steps to the generation of a GDSII file (following a top-down approach).

These tasks will be implemented for different technology libraries and will be realized with different design objectives, such as area, timing, and power consumption. Scripts for these design objectives will also need to be developed. The objective is that by the end of this project the student will have developed an expertise on using these design aids. In addition, the different tradeoffs that are involved in the different steps of a digital circuit design flow, where a variety of design specifications need to be satisfied, will be explored.

The eligibility requirements for this project are

  • VLSI II (EE 431)
  • Knowledge of Cadence, Synopsys tools, and/or SPICE

This project was supervised by Vasilis Pavlidis.

***Archived: This is a past project,  it is not on offer at the moment!***