***Archived: This is a past project, it is not on offer at the moment!***
Background:
Oxide Memories (OxRAMs) are one of the promising candidates for next generation Non-Volatile Memory (NVM) applications. When compared to traditional Flash NVM, OxRAMs have better scalability and faster programming time. While a lot of research effort targets OxRAM-based standalone memories, several unusual applications might be targetted, due to their novel properties. In particular, resistive memories can be technological tuned to exhibit a very low on-resistance or a very high off-resistance, depending on the target application. This opens the possibility to build either good performances or low power non-volatile switches. Such properties has shown a large interest in reconfigurable applications, such as FPGAs, where OxRAMs are used to create non-volatile configurable vias with low impact on data path. By generalizing this approach, OxRAMs might be used to create logic gates with a very low power operation.
Overview:
In this project, we propose to study the use of OxRAMs in co-integration with regular CMOS circuits. Hence, two directions will be explored. First, the student will have to propose an innovative structure of Non-Volatile SRAM memory, in order to provide a generic memory node as fast as SRAM, but with some added non-volatile properties. Then, he/she will explore the opportunity of the OxRAM to build low power logic circuits using a Logic-in-Memory design approach, and try to extend the use of OxRAMs to standard logic computation.
Eligibility requirements:
- Good background in analog design
- Experience with Cadence tools, electrical simulators and verilog-A modeling
- Knowledge in digital design is highly appreciated
References:
[1] G.W. Burr et al., “Overview of candidate device technologies for storage-class-memory,” IBM J. R&D, 52(4/5), 2008.
[2] P.-E. Gaillardon, M. Haykel Ben-Jamaa, M. Reyboz, G. Betti Beneventi, F. Clermidy, L. Perniola, I. O’Connor, “Phase-Change-Memory-Based Storage Elements for Configurable Logic” , International Conference on Field- Programmable Technology (FPT), 8-10 December 2010, Beijing, China.
[3] P.-E. Gaillardon, M. H. Ben-Jamaa, G. Betti Beneventi, F. Clermidy, L. Perniola, “Emerging Memory Technologies for Reconfigurable Routing in FPGA Architecture”, IEEE International Conference on Electronics, Circuits and Systems (ICECS), 12-15 December 2010, Athens, Greece.
[4] S. Matsunaga, J. Hayakawa, S. Ikeda, K. Miura, T. E, H. Ohno, and T. Hanyu, “MTJ-Based Nonvolatile Logic-in- Memory Circuit”, Future Prospects and Issues, IEEE DATE Conference 2009.
This project was supervised by Pierre-Emmanuel Gaillardon.
***Archived: This is a past project, it is not on offer at the moment!***