***Archived: This is a past project, it is not on offer at the moment!***
Background:
Beyond the trend to one-dimensional (1-D) structures, Vertically Stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) are a promising candidate to extend the intrinsic properties of devices. By engineering of the source and drain contacts and by constructing independent double-gate structures, the device polarity can be electrostatically forced to either n- or p-type by polarizing one of the two gates. The in-field polarizability of these devices enables the development of new logic architectures, which are intrinsically not implementable in CMOS in a compact form. In particular, all XOR based gates should be realized with an incredibly small amount of transistors.
To address gate-level routing congestion due to the second gate, the LSI’s SiNW group recently presented an approach for designing an efficient regular layout, called Sea-of-Tiles (SoTs).
Overview:
In this project, we propose to extend the use of regular arrangement of elements from the physical level (SoTs) to the circuit and architectural level. Matrix arrangements of compact logic cells have been demonstrated as a good choice to reduce the impact of inter-gate wiring in reconfigurable circuits. In a first time, the student will have in charge the generalization to these structures to ASIC structures and the study of its impact at the architectural level. In a second time, the student will propose a design methodology as a function of the targeted class of applications and find the optimum structures for arithmetic intensive circuits and control intensive circuits.
Eligibility requirements:
- Good background in digital design
- Experience in digital design flow (Synopsys DC compiler, SoC Encounter, …)
References:
[1] H. Ben Jamaa, K. Mohanram and G. De Micheli, Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis, Design, Automation and Test in Europe, Nice, France, 2009.
[2] S., M. De Marchi, Y. Leblebici, G. De Micheli, “Physical Synthesis onto a Sea-of-Tiles with Double-Gate Silicon Nanowire Transistors,” Design Automation Conference, 2012, To Be Published
[2] P.-E. Gaillardon, M. H. Ben-Jamaa, F. Clermidy, I. O’Connor, “Ultra-Fine Grain FPGAs: A Granularity Study,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 8-9 June 2011, San Diego (CA), 2011.
This project was supervised by Pierre-Emmanuel Gaillardon.
***Archived: This is a past project, it is not on offer at the moment!***