***Archived: This is a past project, it is not on offer at the moment!***
Background:
The LSI’s SiNW group develops new technologies and new design methodologies for emerging devices. Beyond the trend to one-dimensional (1-D) structures, Vertically Stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) are a promising candidate to extend the intrinsic properties of devices. By engineering of the source and drain contacts and by constructing independent double-gate structures, the device polarity can be electrostatically forced to either n- or p-type by polarizing one of the two gates. The in-field polarizability of these devices enables the development of new logic architectures, which are intrinsically not implementable in CMOS in a compact form. In particular, all XOR based gates should be realized with an incredibly small amount of transistors. In addition, they enable the realization of highly regular fabrics. Regular fabrics are mandatory to deal with reliability at nanoscale.
In order to use this higher expressive logic power, it is of our high priority to perform XOR-oriented logic synthesis. However, conventional synthesis tools are based on NAND operation, and lead to poor usage of XOR-intensive functions. This project is intended to develop efficient logic synthesis algorithms for XOR-intensive Regular-fabric-based logic.
Overview:
Common design methodologies use a set of standard cells to implement the fabric and thus perform logic synthesis with this set of small primitives. We propose here to perform logic mapping at finer grain and map logic functions on physical patterns of transistors. To deal with the problem complexity, SAT problem formulation will be used. Thus, the main part of the project will corresponds to translate the problem of technology mapping/routing of logic functions onto regular structures in Boolean conditions. Then, SAT solvers will be employed to map benchmarks of logic functions, and finally comparisons will be performed with regards to standard techniques.
Eligibility requirements:
- Good background in mathematics and computer sciences
- Experience in digital design flow
- Knowledge of SAT formulation problems highly appreciated
References:
[1] H. Ben Jamaa, K. Mohanram and G. De Micheli, Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis, Design, Automation and Test in Europe, Nice, France, 2009.
[2] M. Perkowski and A. Mishchenko, Logic synthesis for regular layout using satisfiability, Proc. Intl Workshop on Boolean Problems, 2002.
[3] S. Devadas, Optimal layout via Boolean satisfiability, Computer-Aided Design, 1989.
[4] G.-J. Nam, K. A. Sakallah, R. A. Rutenbar, Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT, Proceedings of FPGA, 1999.
[5] J. P. Marques-Silva, K. A. Sakallah, GRASP: a search algorithm for propositional satisfiability, Computers,
IEEE Transactions on, May 1999.
This project was supervised by Pierre-Emmanuel Gaillardon.
***Archived: This is a past project, it is not on offer at the moment!***