Definition of a backend process flow using low-k field dielectric for high aspect ratio devices

***Archived: This is a past project,  it is not on offer at the moment!***

**** Master or Semester Project ****

Contact: Dr. Pierre-Emmanuel Gaillardon, Post-doctoral researcher, EPFL-IC-ISIM-LSI

                Mr. Michele De Marchi, Ph.D. candidate, EPFL-IC-ISIM-LSI


Emerging device technologies take advantage of highly efficient structures, including semiconducting fins and nanowire stacks, to enhance transistor channel electrostatics and enable further increase in performance. One disadvantage of these structures is their high topography, i.e., the devices raise tall above the substrate plane. This creates high aspect ratio features, which creates challenges when the devices have to be covered with photoresists for lithography or passivated to proceed with the back-end process flow.

The purpose of the master project is developing a basic one-metal back-end process flow suited to technologies with high aspect ratios. The specific objective is to develop the technology required for contacting vertically-stacked nanowire transistors, then enabling small circuits realization. Low-k H-Si-O based polymer will be used for the passivation. At first, the student will get acquainted with the process steps allowing passivation layer formation and via etching. The student will then investigate the presence of leakage through the passivation, and evaluate methods to reduce this effect. Finally, a good electrical connection to the underlying devices should be guaranteed, through evaluation of different metals and techniques to create via plugs and metal-1 connections. Substrates with complex devices can be made available to the student, when the process will be stabilized.

Further Objectives
Creating areas free of passivation to enable co-integration with other devices, create passivation openings for access to the device channels (e.g., for biosensing applications).

Recommended Skills

  • Basic knowledge in microfabrication and microtechnologies
  • Basic knowledge in EDA (Cadence suite)

***Archived: This is a past project,  it is not on offer at the moment!***