Automatic Mapping of Multi-Processor System-on-Chip (MPSoC) Simulation Descriptions onto FPGA-Based Emulation Frameworks

***Archived: This is a past project,  it is not on offer at the moment!***

Project Description:

With the growing complexity in consumer embedded products, a new-born generation of System-On-Chip (SoC) architectures consisting of complex integrated components communicating with each other at very high-speed rates is being envisioned. One of their main design challenges will be the fast modeling and validation of SoCs consisting of many processing cores (Multi-ProcessingSoC or MPSoC). Currently, MPSoC architectures are mainly tested in transaction and cycle-accurate simulators (using HDL languages and SystemC) to validate their initial behavior. Nevertheless, these complex SW environments are limited in performance (circa 100 Khz) due to signal management overhead. Thus, such environments cannot be used to analyze MPSoC solutions with complex applications. Within this context, it is desirable to transform codes that can initially be simulated in cycle-accurate simulations onto FPGA-based systems that enable much faster prototyping. However, these transformations are very time-consuming and automatic transformations of all possible MPSoC architectures is very difficult with current mechanisms since each group of designers and simulator can use a different MPSoC input description.

The purpose of this project is to provide methods to fill the gap between these two levels of descriptions, namely, cycle-accurate simulation descriptions and FPGA-based synthesizable descriptions. To this end, we need to extend the current SystemC-based MPSoC simulation framework (called MPARM) available at LSI/EPFL from DEIS/University of Bologna to include a correct and automatic translation to the FPGA MPSoC emulation framework also available in LSI/EPFL. In order to perform this work the student needs to study how to efficiently map the automatically generated VHDL/Verilog code from MPSoC descriptions in SystemC using Agility Compiler onto a Xilinx Virtex-II Pro FPGA. Then, the whole MPSoC system needs to be validated by porting the same set of applications available for simulation in MPARM. Therefore, the proposed project implies the use of latest Xilinx hw/sw co-design tools for FPGAs (e.g. Xilinx Embedded Development Kit) and software toolflows for current embedded processors (e.g. GCC crosscompiler for PowerPC), as well as learning the use of Agility Compiler and the cycle-accurate MPARM MPSoC Simulation Framework.

Tasks of the Student:

The tasks expected by the student developing this project are very briefly described in the following:

  • Study of the Xilinx Virtex-II Pro HW/SW toolflow.
  • Study of Agility Compiler HDL code generator from MPSoC SystemC descriptions
  • Study of Xpipes Compiler which includes Agility Compiler to generate simulation MPSoC descriptions.
  • Modification toolflow of Xpipes compiler to generate correct Verilog/VHDL code for the Virtex-II Pro FPGA.
  • Porting of several software benchmarks from MPARM to the MPSoC emulation platform.
  • Implementation and exploration of several MPSoC solutions to verify the correct behaviour of the system.


This project involves knowledge of various aspects of digital system designs. Its requirements are enumerated below:

  • Advanced programming knowledge of the Hardware Design Languages, such as, VHDL or Verilog.
  • Advanced programming knowledge of C code or scripting languages to process text files (e.g. Perl).
  • Basic knowledge is advisable about software development in C and hardware description in SystemC.
  • Basic knowledge about computer architecture and elementary components (e.g. processors, buses, etc.)

***Archived: This is a past project,  it is not on offer at the moment***