New Flow Control Mechanisms for Parallel Links in On-chip Interconnection Networks

***Archived: This is a past project,  it is not on offer at the moment!***

Project Description:

Systems on Chips (SoCs) are high volume and high cost semiconductor products, and have become an integral part of several devices such as cell-phones, video processors, gaming stations, PDAs. With technology advances, several applications are integrated onto a single device. As an example, a cell-phone in near future will have support of high quality TV, online gaming capability, speech recognition system and much more. As the complexity of the SoCs increase, the communication between the various processors and hardware blocks within the SoC chip will become a bottleneck for system performance, as wires do not scale well with technology. To alleviate the communication bottlenecks of current bus-based systems, the use of on-chip interconnection networks, Networks on Chips, has been proposed recently.

One of the characteristic features of the on-chip networks that differentiate them from the chip-to-chip interconnection networks is that the amount of raw wire bandwidth available can be 10 times higher. The purpose of this project is to utilize the large available bandwidth in an efficient manner and tailoring the interconnect to suit the applications. Specifically, the idea is to use multiple parallel links (each link is a set of wires) between adjacent switches of the network, unlike traditional schemes where a single link is used. When a packet arrives at a switch, if multiple links are used, to maximize performance the packet should be dynamically forwarded to one of the links. However, care should be taken to ensure that packets from the same source remain in-order when traversing such parallel links.

In this project, we will present new flow control strategies that allow efficient use of the parallel links, which also guarantee in-order packet delivery at the destination. The strategies should be implemented in two steps: in the first step, they will be implemented on a C++ based network simulator that already has the support for instantiating parallel links. The next step is to implement the strategies and the associated hardware mechanisms in RTL level in SystemC (equivalent of Verilog/VHDL) on existing RTL network simulator.

About the simulators: The C++ simulator is well written and documented, and has been extensively used by LSI group members. The C++ simulator utilizes a global clock and is timing accurate. The simulator evaluates packet latencies, throughput by injecting packets (and sub-units) at each cycle. The RTL simulator has the hardware description of network components and associated tools to build networks.



  • Study the C++/RTL simulators and associated tools.
  • Modification of the C++ simulator to support the new flow control mechanisms.
  • Modification of the RTL simulator to support the mechanisms (refer point 3 in the next section).
  • Perform experiments to quantify the usefulness of the methods.


  • Advanced programming experience in C++.
  • Basic knowledge of computer architecture.
  • For the RTL simulations, knowledge of SystemC (or Verilog/VHDL). If the student has no RTL background, still it could fit for the work on the C++ simulator (just the first part) and additional tasks could be thought if necessary to cover the academic requirements.

***Archived: This is a past project,  it is not on offer at the moment!***