Graphical MPSoC HW/SW Architecture Generator for FPGA-Based MPSoC System Emulation

***Archived: This is a past project,  it is not on offer at the moment!***


Project Description:

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Thus, in order to explore all the possible HW-SW configurations in a MPSoC, cycle-accurate simulation is not practical anymore due to the large timing overhead in simulations, which is the desired level for the extraction of statistics. New methods to extract such fine-grained statistics in a faster way are needed. In this context, LSI has developed a new FPGA-based emulation framework (based on Virtex-II Pro FPGAs) that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. However, this framework requires typically a quite time-consuming process to define different MPSoC architectures since no abstraction from the hardware can be made, conversely to cycle-accurate simulators. In fact, in order to use this emulation platform and build a custom MPSoC, the designer must have a deep knowledge of several Xilinx synthesis tools (EDK and ISE) to select the desired components, and XPIPES (a cross compiler tool to instantiate the interconnection mechanism), and finally manually merge these two parts together to get the final MPSoC system that needs to be downloaded onto the FPGA and can interact with a host pc (e.g. providing/receiving statistics). Hence, tools that simplify the instantiation mechanisms for MPSoC architectures and reduce the amount of knowledge that designers need from the final hardware used on the FPGA are required.

The purpose of this project is to develop a graphical user interface that hides from most of the hardware-related details required by the underlying tools used to build the MPSoC FPGA-based platform (i.e. Xilinx synthesis tools and XPipes interconnection definition). The interface will allow designers to easily select the number and types of components (e.g. number of processing cores and shared memories), the concrete type of interconnection mechanisms (i.e. shared buses or Networks-on-Chip) and the final application that needs to be executed. Then, after this definition process, the whole MPSoC system is automatically assembled and synthesized in a script-like way, without any user interaction. Therefore, the proposed project implies the use of latest Xilinx hw/sw co-design tools for FPGAs (e.g. Xilinx Embedded Development Kit) and software toolflows for current embedded processors (e.g. GCC crosscompiler for PowerPC), as well as learning the use of Xpipes Compiler to generate the interconnection mechanisms.



  • Study the EDK, ISE, XPipes and associated tools.
  • Study the whole design flow of the MPSoC FPGA-Based emulation framework available at LSI/EPFL
  • Analyze each of the components to define templates for each MPSoC component on the FPGA.
  • Definition of signals and interconnections used in the EDK projects for Xilinx Virtex-II Pro FPGAs.
  • Development of a GUI that easily allows the user to build custom MPSoC emulation platforms, without knowledge of the underlying tools, using the previous informations.



  • Advanced programming experience in C, C++ or Java.
  • Basic knowledge of HDL languages (VHDL, Verilog) and scripting languages.
  • Basic knowledge of computer architecture.

***Archived: This is a past project,  it is not on offer at the moment!***