Thermal-Aware Compilation for High-Performance Embedded Architectures

***Archived: This is a past project,  it is not on offer at the moment!***


Project Description:

With the advent of new technology and scaling design parameters, total performance is not the only parameter that needs to be addressed when creating a new design. Power and now temperature are becoming increasingly as important factors as performance, especially in embedded systems. Property vendor compilers do only consider maximum performance when compiling the source code, but do not address the temperature issue.

Temperature has an adverse effect on multiple aspects. It affects the lifetime of the integrated circuit by accelerating the chemical process taking place inside of the chip following Arrhenius equation. Studies show the mean time between failure (MTBF) of an IC is multiplied by a factor 10 for every 300ºC  rise in the junction temperature. Secondly leakage power is becoming the dominant source of power consumption for new process technologies which grow exponentially with temperature. Moreover, temperature has a negative effect on carrier mobility and therefore switching speed of the transistors and thus the overall timing of the circuit. Consequently it is highly desirable to have an even temperature distribution on the chip in order to avoid costly re-design due to timing/temperature as well as simplifying the verification phase. Furthermore, temperature is highly dependent on power consumption, which should be minimized, but depends on multiple factors. In fact, temperature also depends on the placement of the units in the chip. Placing heavy power consuming units close together will intuitively generate an even higher temperature area in the chip as temperature is additive in nature. In contrast, placing power consuming units close to units that have a moderate power consumption will allow the heat generated to dissipate through these units. Other aspects that affect temperature are the execution order of tasks in a unit. Executing tasks one after the other will help the temperature build up whereas spacing the execution of tasks in a unit will allow the unit to have a time to prevent it from heating up. Finally, register assignment is a key factor in the temperature profile of the register file unit. This unit is considered one of the hot points in current architectures, where the number of registers increases rapidly. Consequently, temperature should be addressed as an individual design parameter.

The goal of this project is to improve the effect that register assignment and compiler optimizations have in the temperature profile of the register file and the processor architecture.  For that purpose, a set of high-level optimizations and modifications of the compilation stages will be included in a high-quality compiler. This research will take advantage of the previous work developed in the group in the area of thermal modeling and temperature optimization policies for the processor architecture. The result of this project will enable the temperature-aware (as well as power-aware) compilation as a new optimization level available for the final user.


Tasks :

The tasks expected by the student developing this project are very briefly described in the following:

  • Study of the compilation phases in gcc for high-performance Leon-3 processing architecture.
  • Study of existing thermal and reliability models for the shared register file of the previous architecture..
  • Modification of the register file assignment in gcc to provide thermal-aware register assignment policies.
  • Validation of the proposed policies with real applications in the Leon-3 thermal emulation framework available at LSI.



This project involves knowledge of various aspects of digital system designs, namely:

  • Knowledge of processing architectures and basic knowledge about compilation phases.
  • Advanced programming knowledge of C code.


D. Atienza, et al., “Reliability-Aware Design for Nanometer-Scale Devices”,  Proc. of ASP-DAC, 2008.
K. Patel, et al, “Active Bank Switching for Temperature Control of the RF in a Microproc”, GLSVLSI, 2007.
B. C. Schafer, et al., “Temperature-Aware Compilation for VLIW Processors”, RTCSA, 2007
J. L. Ayala, et al., “Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors”, ICECS, 2006

***Archived: This is a past project,  it is not on offer at the moment!***