Design of innovative systems using oxide memories

***Archived: This is a past project,  it is not on offer at the moment!***

**** Master or Semester Project ****

Contact: Dr. Pierre-Emmanuel Gaillardon, Post-doctoral researcher, EPFL-IC-ISIM-LSI

Background of the project   
Oxide Memories (OxRAMs) are one of the promising candidates for next generation Non-Volatile Memory (NVM) applications. When compared to traditional Flash NVM, OxRAMs have better scalability and faster programming time. While a lot of research effort investigates OxRAM-based standalone memories, several unusual applications might be targetted, exploiting the associated properties. In particular, resistive memories can be technological tuned to exhibit a very low on- resistance or a very high off-resistance, depending on the target application. This opens the possibility to build either good performances or low power non-volatile switches. Such properties have shown a large interest in reconfigurable applications, such as FPGAs, where OxRAMs are used to create non- volatile configurable vias with low impact on data path. By generalizing this approach, OxRAMs might be used to create logic architectures with a very low power operation.

Overview of the project   
In this project, we propose to study the use of OxRAMs in co-integration with regular CMOS circuits, in order to realize low-power digital-applications-oriented circuits. Hence, two directions will be explored. First, the student will have to propose an innovative circuit structure able to exploit the routing interest of OxRAM. In particular, coarse-grain digital co-processors will be targeted. Then, the student will design novel computation elements that rely of OxRAM to make energy-efficient computation. The final objective is to quantify the performance gains (area, delay, power) leveraged by the proposed technique.

Eligibility requirements   

  • Good background in digital design
  • Experience with Synopsis DC tool
  • Knowledge in machine-learning is highly appreciated
  • Experience with Cadence tools, electrical simulators and verilog-A modeling is a plus



[1]    G.W. Burr et al., “Overview of candidate device technologies for storage-class-memory,” IBM J. R&D, 52(4/5), 2008.
[2]    P.-E. Gaillardon et al., “Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs”, IEEE Transactions on Nanotechnology, vol. 12, no. 1, pp. 40-50, January 2013.

***Archived: This is a past project,  it is not on offer at the moment!***