Design and implementation of a data-path FPGA

***Archived: This is a past project,  it is not on offer at the moment!***

**** Master or Semester Project ****

Contact: Dr. Pierre-Emmanuel Gaillardon, Post-doctoral researcher, EPFL-IC-ISIM-LSI


Background of the project   
Reconfigurable Circuits, such as Field Programmable Gate Arrays (FPGA) are versatile circuits that are more and more appreciated in industry. However, FPGAs are really efficient in implementing control-oriented logic functions, and suffers from their internal structure when it comes to the realization of arithmetic circuits.

Recently, the Integrated Systems Laboratory demonstrated novel logic synthesis methodologies suited to the design of arithmetic circuits. In particular, a new data representation structure, called Biconditional Binary Decision Diagrams (BBDDs) has been proven to be really compact both in terms of function representation and in terms of direct circuit transcription.

Overview of the project   
In this project, we propose to leverage the interest of BBDDs for the design of a novel architecture of FPGA logic block suited to arithmetic operation. Here, instead of providing a block with dedicated arithmetic circuits, we expect to design the equivalent of a LUT for arithmetic operation. The designed logic block will then be used in a complete FPGA architecture and the circuit level performances of such a structure will be evaluated through architectural benchmarking.

Eligibility requirements   

  • Good background in digital design
  • Proficiency in C/C++
  • Knowledge of the FPGA architecture is a plus



[1]    L. Amarù, P.-E. Gaillardon, G. De Micheli, “Biconditional BDD: A New Canonical BDD for Logic Synthesis targeting Ambipolar Transistors”, Design, Automation & Test in Europe Conference (DATE), 18-22 March 2013, Grenoble, France.

***Archived: This is a past project,  it is not on offer at the moment!***