Thesis title: Fabrication and Design of Nanoscale Regular Circuits
Fabrication and Design of Nanoscale Regular Circuits
PhD Thesis, M. Haykel Ben Jamaa
Giovanni De Micheli, Director
Yusuf Leblebici, Director
Lausanne: EPFL, 2009.
During many decades, Moore’s law, which predicts an exponential increase in performance of semiconductor logic circuits and memories and an exponential decrease in their area, has proven its universal validity. It also helped the semiconductor industry predict and structure its future growth and organize its research focuses in a more visible and synergetic way. Simultaneously, the continuous growth of global demand with respect to semiconductor products (connectivity, security, healthcare, energy, entertainment, etc.) spanned a larger field where the impact of Moore’s law could be observed. The scaling of electronic devices is facing today several physical and economic obstacles, including the difficulty of adapting lithography tools, maintaining good device performance and ensuring a reliable design with the continuously shrinking device features. Several solutions have been proposed at both manufacturing and system levels in order to address this situation. Some emerging technologies based on quasi one- and zero-dimensional structures are promising candidates to succeed complementary metal-oxide-semiconductor (CMOS) technology. These technologies, for instance silicon nanowires (SiNWs) and carbon nanotubes (CNTs), share some aspects, including high variability and regular organization. The assessment of their benefits requires an interdisciplinary approach, so that technological challenges and opportunities can be leveraged at the design level. This dissertation is a new interdisciplinary vision in the field of emerging technologies. The work in this thesis is done at three levels. At the technology level, a novel fabrication technique for silicon nanowire crossbars is demonstrated, whereby the goal is to show the ability to use CMOS-compatible and only standard photolithography steps in order to achieve a sub-lithographic pitch. At the system level, the crossbar decoder design is optimized by developing new families of encoding schemes, which enhance the decoder fault-tolerance and save area. A testing procedure for this circuit part is also developed, aiming at the introduction of a novel concept of design for test in nanowire crossbar technologies. At the logic design level, the ambipolarity of carbon nanotube field effect transistors (CNTFETs) is leveraged by designing a novel library of CNTFET logic gates, which are used in logic synthesis, proving the higher expressive power and compactness of CNTFET technology compared with CMOS.